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|Designed by||ARM Holdings|
|Instruction set||ARM (32-bit), Thumb (16-bit) (optional), Thumb-2 (optional)|
The ARM11 microarchitecture (announced 29 April 2002) introduced the ARMv6 architectural additions which had been announced in October 2001. These include SIMD media instructions, multiprocessor support and a new cache architecture. The implementation included a significantly improved instruction processing pipeline, compared to previous ARM9 or ARM10 families, and is used in smartphones from Apple, Nokia, and others. The initial ARM11 core (ARM1136) was released to licensees in October 2002.
The ARM11 family are currently the only ARMv6-architecture cores. There are, however, ARMv6-M cores (Cortex-M0 and Cortex-M1), addressing microcontroller applications; ARM11 cores target more demanding applications.
Differences from ARM9
In terms of instruction set, ARM11 builds on the preceding ARM9 generation. It incorporates all ARM926EJ-S features and adds the ARMv6 instructions for media support (SIMD) and accelerating IRQ response.
Microarchitecture improvements in ARM11 cores include:
- SIMD instructions which can double MPEG-4 and audio digital signal processing algorithm speed
- Cache is physically addressed, solving many cache aliasing problems and reducing context switch overhead.
- Unaligned and mixed-endian data access is supported.
- Reduced heat production and lower overheating risk
- Redesigned pipeline, supporting faster clock speeds (target up to 1 GHz)
- 64-bit data paths
JTAG debug support (for halting, stepping, breakpoints, and watchpoints) was simplified. The EmbeddedICE module was replaced with an interface which became part of the ARMv7 architecture. The hardware tracing modules (ETM and ETB) are compatible, but updated, versions of those used in the ARM9. In particular, trace semantics were updated to address parallel instruction execution and data transfers.
ARM makes an effort to promote good[by whom?] Verilog coding styles and techniques. This ensures semantically rigorous designs, preserving identical semantics throughout the chip design flow, which included extensive use of formal verification techniques. Without such attention, integrating an ARM11 with third-party designs could risk exposing hard-to-find latent bugs. Due to ARM cores being integrated into many different designs, using a variety of logic synthesis tools and chip manufacturing processes, the impact of its register-transfer level (RTL) quality is magnified many times. The ARM11 generation focused more on synthesis than previous generations, making such concerns be more of an issue.
There are four ARM11 cores:
- ARM1156, introduced Thumb2 instructions
- ARM1176, introduced security extensions
- ARM11MPcore, introduced multicore support
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- Ambarella A5s, A7, A7L
- ASPEED Technology Inc. AST25xx
- Broadcom BCM2835 (Raspberry Pi), BCM21553
- Cavium ECONA CNS3000 series 
- CSR Quatro 4230, 45xx, 53xx
- Freescale Semiconductor i.MX3x series, such as i.MX31, i.MX35
- Nintendo CTR-CPU (Nintendo 3DS CPU)
- Infotmic IMAPX2xx
- Nvidia Tegra
- PLX Technology NAS782x
- MediaTek MTK6573
- Qualcomm MSM720x, MSM7x27
- Qualcomm Atheros AR7400
- Samsung S3C64xx, S5P64xx, S5L87xx, S5L89xx or Exynos Dual with Logic11
- Telechips TCC8902
- Xcometic KVM2800
- Texas Instruments OMAP2 series, with a TMS320 C55x or C64x DSP as a second core
- not supported by Linux as of version 3.3
- "The ARM11 Microarchitecture", ARM Ltd, 2002
- The Dangers of Living with an X (bugs hidden in your Verilog), Version 1.1 (14 October 2003).
- ARM1136JF-S and ARM1136J-S Technical Reference Manual Revision: r1p5; ARM DDI 0211K
- ARM1176JZF-6 Technical Reference Manual Revision: r0p7; accessed on 4 October 2012.
- "Cavium Networks Introduces ECONA Family of Super Energy Efficient ARM®-Based System-on-Chip (SoC) Processors for the Digital Home that break the 1 Watt Barrier" (Press release). Cavium. September 8, 2009.
- ARM Holdings
- Official website
- ARM11 Technical Reference Manuals
- ARMv6 Architecture Reference Manual (requires registration)
- Quick Reference Cards
- Instructions: Thumb (1), ARM and Thumb-2 (2), Vector Floating Point (3)
- Opcodes: Thumb (1, 2), ARM (3, 4), GNU Assembler Directives 5.
- ARM11 lacks an integer hardware division instruction
- Yurichev, Dennis, "An Introduction To Reverse Engineering for Beginners" including ARM assembly. Online book: http://yurichev.com/writings/RE_for_beginners-en.pdf
- The ARM11 Architecture, 2009, by Ian Davey and Payton Oliveri